The present invention relates to semiconductor devices, and more particularly to flash memory devices having an enhanced gate coupling ratio.
Flash memory devices are known in the art. For example, U.S. Pat. No. 6,897,116 (Lee et al., “the '116 patent”) discloses an embodiment of a flash memory device having an enhanced gate coupling ratio (GCR). The concept of gate coupling ratio is discussed in the '116 patent, and that discussion is incorporated herein by reference. A method of manufacturing a flash memory device having an enhanced gate coupling ratio which 1) provides greater flexibility of the manufacturing process and 2) does not require reduction of buried drain semiconductor space would be desirable.